Transistor formation for semiconductor devices

ABSTRACT

A semiconductor fabrication method of forming a pair of transistor gates of opposite conductivity type by partially forming first and second gate stacks comprising an insulation layer, a conductive layer and polysilicon layer for the pair of transistor by removing a portion of the polysilicon layer. The polysilicon layer includes a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants. A first-type conductive transistor gate is formed by, completing the formation of the first gate stack and a second-type conductive transistor gate is formed by completing the formation of the second gate stack separately from the formation of the first-type transistor gate.

FIELD OF THE INVENTION

[0001] This invention relates to a semiconductor device and fabrication thereof and, more particularly, to transistor formation in a semiconductor device and fabrication thereof.

BACKGROUND OF THE INVENTION

[0002] Semiconductor devices, including logic devices, embedded memory devices and memory devices, utilize Field Effect Transistors (FETs), which may use both N+ and P+ doped polysilicon gates. However, using both types of transistor gates in the same device creates challenges in the fabrication process. Many memory devices utilize both N+ and P+ polysilicon gates and thus exhibit fabrication issues that require attention to obtain quality devices at the lowest production price possible.

[0003] For example, during Static Random Access Memory (SRAM) fabrication, when both N+ and P+ polycrystalline silicon (or germanium) are used as the transistor gate electrodes (known in the art as wordline gate electrodes), it is difficult to form good wordline etch profiles for both N-channel and P-channel transistors without pitting the silicon substrate, due to the different etching characteristics of a P-type doped polysilicon versus an N-type doped polysilicon.

[0004] The difficulty increases when thinner gate oxide is used fabricate smaller geometric devices. Furthermore, if a Self Aligned Contact (SAC) etch is desired to open access to the source/drain areas of the transistor, it requires a tall wordline stack with an oxide/nitride cap deposited on top of the wordline gate electrodes. The taller wordline stack used for a process flow with SAC etch makes it more difficult to etch than process flows that use a salicide process due to the higher aspect ratio during the etch process. For example, the SAC etch has to etch through the entire gate stack comprising an oxide (or nitride) cap, a WSi_(x) (or W) layer and a polysilicon layer. On the other hand a silicide process needs to only etch through a polysilicon layer.

[0005] The present invention comprises a method to form transistors with highly desirable transistor gate profiles.

SUMMARY OF THE INVENTION

[0006] A significant focus of an exemplary implementation of the present invention includes a method of forming transistors, such as p-channel and n-channel devices, during v semiconductor fabrication.

[0007] An exemplary implementation of the present invention comprises a semiconductor fabrication method of forming a pair of transistor gates of opposite conductivity type by partially forming first and second gate stacks comprising an insulation layer, a conductive layer and polysilicon layer for the pair of transistor by removing a portion of the polysilicon layer. The polysilicon layer includes a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants. A first-type conductive transistor gate is formed by, completing the formation of the first gate stack and a second-type conductive transistor gate is formed by completing the formation of the second gate stack separately from the formation of the first-type transistor gate.

BRIEF DESCRIPTION OF THE DRAWING

[0008]FIG. 1 is a cross-sectional view of a semiconductor substrate section showing an overlying gate oxide layer, a conductively doped polysilicon layer, a tungsten silicide layer and an oxide capping layer.

[0009]FIG. 2 is a subsequent cross-sectional view taken from FIG. 1 following the a partial etch to form a pair of partial wordline stacks, each partial stack comprising an oxide cap, a tungsten silicide intermediate layer and conductively doped polysilicon.

[0010]FIG. 3 is a subsequent cross-sectional view taken from FIG. 2 following an N+ polysilicon etch followed by a Halo/source-drain extension implant.

[0011]FIG. 4 is a subsequent cross-sectional view taken from FIG. 3 following a P-channel Halo photo.

[0012]FIG. 5 is a subsequent cross-sectional view taken from FIG. 4 after a P+ polysilicon etch followed by a P-channel Halo implant.

[0013]FIG. 6 is a subsequent cross-sectional view taken from FIG. 5 after the photoresist is removed.

DETAILED DESCRIPTION OF THE INVENTION

[0014]FIG. 1 depicts a conventionally processed semiconductor assembly prior to implementation of the present invention. FIGS. 2-6 depict an exemplary implementation of the present invention that is directed to a method to form transistor pairs for use in semiconductor devices.

[0015] In conventional processing flows used to form a transistor gate and the transistor's source/drain regions, a gate oxide is deposited, followed by the deposition of a polysilicon layer. Next, the polysilicon layer is patterned using photolithography, to allow the implanting of n-type conductive dopants to form N+ polysilicon. Next, the polysilicon layer is patterned using photolithography, to allow the implanting of p-type conductive dopants to form P+ polysilicon. Next, a conductive layer, such as WSi_(x) or WN/W is deposited to complete a stack of material that will be patterned and etched together with the N+ polysilicon and P+ polysilicon to form an N+ polysilicon gate and a P+ polysilicon gate. The etch will stop in the gate oxide layer.

[0016] Prior to the patterning and etching of the N+ and P+ polysilicon gates the present invention departs from conventional processing flows and includes a new process sequence that greatly improves the quality of the resulting N-channel and P-channel transistors.

[0017] The following exemplary implementation is in reference to a fabrication of transistor pairs for use in a semiconductor assembly. While the concepts of the present invention are conducive to the fabrication of transistor pairs for a Static Random Access Memory (SRAM) device, the concepts taught herein may be applied to other semiconductor devices, such as Dynamic Random Access Memories (DRAMs), logic devices and embedded memory devices, that would likewise benefit from the use of the transistor pair fabrication process disclosed herein. Therefore, the depictions of the present invention in reference to SRAM transistor pair formation are not meant to so limit the extent to which one skilled in the art might apply the concepts taught hereinafter.

[0018] Using methods know to those skilled in the art and referring now to FIG. 1, a gate oxide layer 11 has been formed on substrate 10, such as a silicon substrate, over which a conductively doped polysilicon layer, comprising N+ polysilicon section 13 and P+ polysilicon section 14 has been formed. Conductive layer 15, such as tungsten silicide (WSi_(x)), tungsten nitride (WN) or tungsten (W) has been formed over N+ polysilicon section 13 and P+ polysilicon section 14, over which, capping layer 16, such as oxide or nitride, has been formed.

[0019] Referring now to FIG. 2, an etch step, such as an insitu dry etch, is preformed to pattern and partially form a wordline pair comprising N+ polysilicon wordline 27 and P+ polysilicon wordline 28. As an example, during this partial etch wordline stack 27, comprising oxide cap 25, WSi_(x) 23 and N+ polysilicon 21 and wordline stack 28, comprising oxide cap 26, WSi_(x) 24 and N+ polysilicon 22, are formed. This etch step is a partial etch in that only a portion of N+ polysilicon section 13 and a portion of P+ polysilicon section 14 are removed to form N+ polysilicon structure 21 and P+ polysilicon structure 22, respectively. Performing this partial etch is an important step to the process method of the present invention that will become evident in the subsequent step.

[0020] Typically, WSi_(x) is etched by Cl₂ and CF₄, while WN and W are etched by NF₃ and Cl₂. The etch is timed such that it will stop after partial sections of polysilicon section 13 and polysilicon section 14 are removed. A WSi_(x) etch (or a W/WN etch) can end point easily; thus, a requirement of the present invention is for a complete removal of the WSi_(x) (or W/WN) and partially etching into the polysilicon layers 13 and 14.

[0021] Referring now to FIG. 3, photoresist mask 30 is patterned to cover P+ polysilicon 14 and to encompass and cover wordline stack 28, prior to a subsequent etch step. Next, an N+ polysilicon etch is performed to remove exposed N+ polysilicon 13 to complete the profile of wordline stack 27, comprising oxide cap 25, WSi_(x) 23 and N+ polysilicon 31. The N+ polysilicon etch is selective to polysilicon and will therefore stop on oxide cap 25 and gate oxide 12. An example of a chemistry, which may be used to etch the N+ polysilicon but not the oxide, is HBr, Cl₂ and O₂.

[0022] The N+ polysilicon etch is followed by a halo implant, such as an angled halo implant using boron impurities, such as Boron (B₁₁), to form doped drain regions 32. Next, a Source/Drain Extension (SDE) implant step is performed, such as a Lightly Doped Drain (LDD) implant step using arsenic (As) impurities, to create lightly doped drain regions 33 and thus to complete the formation of an n-channel transistor.

[0023] For example, the halo implant may be performed by implanting the substrate with 30 keV boron ions to a dose of 2e12 ions/cm² at a tilt angle of 25° from four directions with a 90° rotation angle (or X4), while the SDE implant may be performed by implanting the substrate with 15 keV arsenic ions to a dose of 5e13 ions/cm² at an angle of 25° X4.

[0024] Referring now to FIG. 4, photoresist mask 40 is patterned to cover wordline stack 27, prior to a subsequent etch step. It is desirable that photoresist mask 40 under-laps P+ polysilicon 14 such that the entire substantially vertical edge of P+ polysilicon 14 is exposed to the above mentioned etch step so that no polysilicon material remains at the N+ poly/P+ poly interface.

[0025] Referring now to FIG. 5, a P+ polysilicon etch is performed to remove exposed P+ polysilicon 14 and to complete the profile of wordline stack 28, comprising oxide cap 26, WSi_(x) 24 and P+ polysilicon 50. The P+ polysilicon etch is selective to polysilicon and will therefore stop on oxide cap 26 and gate oxide 12. An example of a chemistry, which may be used to etch the P+ polysilicon but not the oxide, is HBr, Cl₂ and O₂.

[0026] Following the P+ polysilicon etch step, a halo implant, such as an angled phosphorus halo implant, is performed to form source/drain regions 52 and thus to complete the formation of a p-channel transistor. The implant may be performed by implanting the substrate with 80 keV phosphorous ions to a dose of 2e12 ions/cm at an angle of 25° X4.

[0027] Referring now to FIG. 6, a final etch step is performed to remove photoresist mask 40. Fabrication methods known to those skilled in the art are then used to complete the processing of the memory device. The fabrication method used to form the wordline pair may be used in numerous semiconductor applications and particularly in, but not limited to, SRAMs. For example, this fabrication method may also be implemented to fabricate transistor gate electrodes (i.e., gate polysilicon) in other semiconductor devices, such as logic devices and embedded memory devices.

[0028] It is to be understood that, although the present invention has been described with reference to a preferred embodiment, various modifications, known to those skilled in the art, may be made to the disclosed structure and process herein without departing from the invention as recited in the several claims appended hereto. 

What is claimed is:
 1. A method of forming a pair of transistor gates of opposite conductivity type during semiconductor fabrication comprising the steps of: partially forming first and second gate stacks comprising an insulation layer, a conductive layer and a polysilicon layer for said pair of transistor by removing a portion of said polysilicon layer, said polysilicon layer having a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants; forming a first-type conductive transistor gate by completing the formation of said first gate stack; forming a second-type conductive transistor gate by completing the formation of said second gate stack; wherein said steps of forming a first-type conductive transistor gate and a second-type conductive transistor gate are performed separately.
 2. The method of claim 1, wherein said step of partially forming said first and second gate stacks further comprises etching into, but not through, said polysilicon layer.
 3. The method of claim 2, wherein said etching into, but not through, said polysilicon layer comprises a timed etch that is selective to polysilicon material.
 4. A method of forming a pair of transistor gates of n-type and p-type conductivity during semiconductor fabrication comprising the steps of: partially forming first and second gate stacks comprising an insulation layer, a conductive layer and a polysilicon layer for said pair of transistor by removing a portion of said polysilicon layer, said polysilicon layer having a dominant region of N+ type conductive dopants and a dominant region of P+ type conductive dopants; forming a N+ type conductive transistor gate by completing the formation of said first gate stack; forming a P+ type conductive transistor gate by completing the formation of said second gate stack; wherein said steps of forming a N+ type conductive transistor gate and a P+ type conductive transistor gate are performed separately.
 5. The method of claim 4, wherein said step of partially forming said first and second gate stacks further comprises etching into, but not through, said polysilicon layer.
 6. The method of claim 5, wherein said etching into, but not through, said polysilicon layer comprises a timed etch that is selective to polysilicon material.
 7. A method of forming a pair of transistors of opposite conductivity type during semiconductor fabrication comprising the steps of: partially forming first and second gate stacks comprising an insulation layer, a conductive layer and a polysilicon layer for said pair of transistor by removing a portion of said polysilicon layer, said polysilicon layer having a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants; forming a first-type conductive transistor by completing the formation of said first gate stack and forming source/drain regions dominated with said first-type conductive dopants; forming a second-type conductive transistor by completing the formation of said second gate stack and forming source/drain regions dominated with said second-type conductive dopants; wherein said steps of forming a first-type conductive transistor and a second-type conductive transistor are performed separately.
 8. The method of claim 7, wherein said step of partially forming said first and second gate stacks further comprises etching into, but not through, said polysilicon layer.
 9. The method of claim 8, wherein said etching into, but not through, said polysilicon layer comprises a timed etch that is selective to polysilicon material.
 10. A method of forming a pair of transistors of opposite conductivity type during semiconductor fabrication comprising the steps of: etching at least two stacks of material, a first stack comprising a gate oxide layer underlying a first-type conductive polysilicon material covered with a conductive material and a second stack comprising said gate oxide layer underlying a second-type conductive polysilicon material covered with a conductive material, said etching step stopping in said first-type and second-type conductive polysilicon materials; patterning a first-type transistor region; etching said first-type conductive polysilicon and stopping said etch in said gate oxide layer; implanting said first-type transistor region with first-type conductive dopants; patterning a second-type transistor region; etching said second-type conductive polysilicon and stopping said etch in said gate oxide layer; implanting said second-type transistor region with second-type conductive dopants.
 11. The method of claim 10, wherein said step of partially forming said first and second gate stacks further comprises etching into, but not through, said polysilicon layer.
 12. The method of claim 11, wherein said etching into, but not through, said polysilicon layer comprises a timed etch that is selective to polysilicon material.
 13. A method of forming a pair of complementary transistors during semiconductor fabrication of a memory device comprising the steps of: etching at least two stacks of material, a first stack comprising a gate oxide layer underlying an N+ type conductive polysilicon material covered with a metal material, and a second stack comprising said gate oxide layer underlying a P+ type conductive polysilicon material covered with said metal material, said etching step stopping in said N+ and P+ type conductive polysilicon materials; patterning an n-channel transistor region; etching said N+ type polysilicon and stopping said etch in said gate oxide layer; implanting said n-channel transistor region with n-type conductive dopants; patterning a p-channel transistor region; etching said P+ type polysilicon and stopping said etch in said gate oxide layer; implanting said p-channel transistor region with p-type conductive dopants.
 14. The method of claim 13, wherein said step of partially forming said first and second gate stacks further comprises etching into, but not through, said polysilicon layer.
 15. The method of claim 14, wherein said etching into, but not through, said polysilicon layer comprises a timed etch that is selective to polysilicon material.
 16. A method of forming complementary transistors during semiconductor fabrication of a memory device comprising the steps of: performing an insitu dry etch of a P+ polysilicon layer and an N+ polysilicon layer to pattern and partially form a wordline pair comprising an N+ polysilicon wordline and a P+ polysilicon wordline, said N+ polysilicon wordlines further comprising a first tungsten material and a first oxide material and said P+ polysilicon wordlines further comprising a second tungsten material and a second oxide material; masking said P+ polysilicon layer and said P+ polysilicon wordline and exposing said N+ polysilicon layer; etching said exposed N+ polysilicon layer to form a complete profile of said N+ polysilicon wordline comprising said N+ polysilicon layer, said first tungsten material and said first oxide material; performing a first halo implant to form n-type conductively doped drain regions for n-channel transistors; performing a Source/Drain Extension (SDE) implant to form n-type conductive lightly doped drain regions for said n-channel transistors; masking said N+ polysilicon wordline and exposing said P+ polysilicon layer; etching said exposed P+ polysilicon layer to form a complete P+ polysilicon wordline profile comprising said P+ polysilicon layer, said second tungsten material, and said second oxide material; performing a second halo implant to form p-type conductively doped source/drain regions for p-channel transistors.
 17. The method as recited in claim 16, wherein said insitu dry etch step further comprises a partial etch to remove only a portion of said N+ polysilicon layer and only a portion of said P+ polysilicon layer.
 18. The method as recited in claim 17, wherein said insitu dry etch step further comprises a Cl₂ and CF₄ etch chemistry to etch a tungsten silicide material.
 19. The method as recited in claim 17, wherein said insitu dry etch step further comprises a NF₃ and Cl₂ etch chemistry to etch a tungsten nitride material or tungsten material.
 20. The method as recited in claim 17, wherein said insitu dry etch step is timed such that it will stop after partial portions of said N+ polysilicon layer and P+ polysilicon layer are removed.
 21. The method as recited in claim 17, wherein said first halo implant step comprises an angled halo implant using boron impurities.
 22. The method as recited in claim 21, wherein said boron impurities comprise Boron (B₁₁).
 23. The method as recited in claim 21, wherein said first halo implant step comprises implanting with 30 keV boron ions to a dose of 2e12 ions/cm² at a tilt angle of 25° from four directions with a 90° rotation angle.
 24. The method as recited in claim 17, wherein said Lightly Doped Drain (LDD) implant step comprises an implant using arsenic (As) impurities.
 25. The method as recited in claim 24, wherein said Lightly Doped Drain (LDD) implant step comprises implanting with 15 keV arsenic ions to a dose of 5e13 ions/cm² at a tilt angle of 25° from four directions with a 90° rotation angle.
 26. The method as recited in claim 17, wherein said masking of said N+ polysilicon layer under-laps said P+ polysilicon such that the entire substantially vertical edge of said P+ polysilicon is exposed prior to said step of etching P+ polysilicon layer.
 27. The method as recited in claim 17, wherein said second halo implant step comprises an angled halo implant using phosphorus impurities.
 28. The method as recited in claim 27, wherein said second halo implant step comprises implanting the substrate with 80 keV phosphorous ions to a dose of 2e12 ions/cm² at a tilt angle of 25° from four directions with a 90° rotation angle. 